➊
Improvement of characteristics
of CVD graphene electronic device using passivation layer
➊
Improvement of characteristics of CVD graphene
electronic device using passivation layer
|
[ Measurement result ]
[ Analysis ]
Mechanism of the effects of low temperature Al2O3 passivation on graphene field effect transistors
C.G. Kang, et al., Carbon, 53, 2013, p.182
➋
Development of characteristic analysis model for CVD graphene electronic device
Two trap model : | Physical mechanisms affecting the hsteretic behavior of graphene devices. Black dashed lines in Al₂O₃ layer represent the grain boundary. Lower schematic is a magnification of red circled region in the upper schematic, showing the mechanism of charge trapping at the top and bottom interface of graphene. The gap at the interface is exaggerated to emphasize the role of trapped air molecules. (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.) |
➋
Development of characteristic analysis model
for CVD graphene electronic device
Two trap model : | Physical mechanisms affecting the hsteretic behavior of graphene devices. Black dashed lines in Al₂O₃ layer represent the grain boundary. Lower schematic is a magnification of red circled region in the upper schematic, showing the mechanism of charge trapping at the top and bottom interface of graphene. The gap at the interface is exaggerated to emphasize the role of trapped air molecules. (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.) |
Quantitative analysis of hysteretic reactions at the interface of graphene and SiO2 using the short pulse I-V method
Y.G. Lee, et al., Carbon, 60, 2013, p.453
➌
Stabilization of device characteristics
using standard process technology
Schematic diagram of back-gated graphene FET device fabrication
(Heat treatment for stabilization of device characteristics at each stage of the process)
➊Channel Patterning
(Au hardmask)
➋Graphene etching
➌No process
S/D patterning
➍Pre-annealing
48h@vacuum & annealing(250℃, 2h)
➎Passivation
Al₂O₃ 30mm@130℃ using ALD
➏Final annealing
300℃, 1h@vacuum
➊Channel Patterning
(Au hardmask)
➋Graphene etching
➌No process
S/D patterning
➍Pre-annealing
48h@vacuum & annealing(250℃, 2h)
➎Passivation
Al₂O₃ 30mm@130℃ using ALD
➏Final annealing
300℃, 1h@vacuum
Comparison of final device characteristics
according to heat treatment
Verification of long-term operation stability of
a device manufactured using a standard process
Comparison of final device characteristics according to heat treatment
Verification of long-term operation stability of
a device manufactured using a standard process
A facile process to achieve hysteresis-free and fully stabilized graphene field-effect transistors
Y.J. Kim, et al., Nanoscale, 7, 2015, p.4013
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TEL +82-54-727-0822
FAX +82-54-279-5029
Support@alphagraphene.com