Besides the CVD graphene transfer process,
are there other process factors that affect device performance?
Besides the CVD graphene transfer process, are there other process factors that affect device performance?
Top gate graphene FET fabrication process schematic
Substrate preparation
➊Substrate preparation
Graphene transfer
➋Graphene transfer
Electrode metal deposition & patterning
➌Electrode metal deposition & patterning
Gate dielectric deposition
➍Gate dielectric deposition
Gate metal deposition & patterning
➎Gate metal deposition & patterning
Substrate preparation
➊Substrate preparation
Graphene transfer
➋Graphene transfer
Electrode metal deposition & patterning
➌Electrode metal deposition & patterning
Gate dielectric deposition
➍Gate dielectric deposition
Gate metal deposition & patterning
➎Gate metal deposition & patterning
➊
To ensure proper operation of graphene electronics, it is crucial to be knowledgeable about the interfaces and control conditions that are required.
➊
To ensure proper operation of graphene electronics, it is crucial to be knowledgeable
about the interfaces and control conditions that are required.
※ Scroll left and right to check
Interface | Graphene-2D/metal | Graphene -2D/Semiconductor | Graphene - 2D/dielectric |
---|---|---|---|
Charge transfer properties | • Charge injection | • Schottky contact • Tunneling | • Ballistic carrier transport |
Main control condition | • Electrostatic distance • Band align | • Schottky barrier height • Graphene Fermi level | • Length of mean free path • Surface and charged impurity scattering |
➋
Structure modification of CVD graphene electronic devices can
lead to significant improvements in their characteristics
➋
Structure modification of CVD graphene electronic devices can lead to significant improvements in their characteristics
Buried-gate Graphene FET
Top-gate Graphene FET
Equivalent circuit model of graphene channel region
Buried-gate Graphene FET
Top-gate Graphene FET
Drain current modeling equation | ![]() | ![]() |
Electric field contour in device by biased gate
Buried-gate GFET : 3D view |
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Buried-gate GFET : Top view of graphene |
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Top-gate GFET : 3D View |
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Top-gate GFET : Top view of graphene |
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Advantages of a buried-gate structure for graphene field-effect transistor
S.K. Lee, Y.J.Kim, et al., Semiconductor Science and Technology, 34, 2019, 055010
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