Besides the CVD graphene transfer process,

are there other process factors that affect device performance?

Besides the CVD graphene transfer process, are there other process factors that affect device performance?

Top gate graphene FET fabrication process schematic

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To ensure proper operation of graphene electronics, it is crucial to be knowledgeable about the interfaces and control conditions that are required.

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To ensure proper operation of graphene electronics, it is crucial to be knowledgeable
about the interfaces and control conditions that are required.

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Interface
Graphene-2D/metal
Graphene -2D/Semiconductor
Graphene - 2D/dielectric
Charge transfer properties
• Charge injection
• Schottky contact
• Tunneling
• Ballistic carrier transport
Main control condition
• Electrostatic distance

• Band align

• Schottky barrier height
• Graphene Fermi level

• Length of mean free path
• Surface and charged impurity scattering


Structure modification of CVD graphene electronic devices can
lead to significant improvements in their characteristics


Structure modification of CVD graphene electronic devices can lead to significant improvements in their characteristics

Buried-gate Graphene FET


Top-gate Graphene FET


Equivalent circuit model of graphene channel region

Buried-gate Graphene FET


Top-gate Graphene FET


Drain current modeling equation
Drain current modeling equation

Electric field contour in device by biased gate 


Buried-gate GFET : 3D view



Buried-gate GFET : Top view of graphene



Top-gate GFET : 3D View



Top-gate GFET : Top view of graphene


Advantages of a buried-gate structure for graphene field-effect transistor

S.K. Lee, Y.J.Kim, et al., Semiconductor Science and Technology, 34, 2019, 055010

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Alpha Graphene Inc.

#403, Business Innovation Center for Advanced Technology, 77,

Cheongam-ro, Nam-gu, Pohang-si, Gyeongsangbuk-do, Republic of Korea, 37673


TEL  +82-54-727-0822

FAX  +82-54-279-5029

Support@alphagraphene.com


ⓒ 2023 ALPHAGRAPHENE. All Rights Reserved.